The field of the invention is that of integrated circuit processing in the submicron range.
Defining the gate length for a MOSFET integrated circuit involves patterning a layer of material for the gates, usually polycrystalline silicon (poly), as uniformly as possible and usually to as small a dimension as possible, given that the art constantly drives to smaller linewidths.
Some attempts have been made in a hard mask process to define the resist at minimum linewidth and then reduce the resist laterally by a dry etch before etching the hardmask. Other attempts have been made to etch the hard mask and then reduce it laterally before using the hardmask to etch the poly gate layer.
There have been problems with the quality of the edge definition of the hardmask in such approaches.
In addition, there is a geometric problem that applies to circuits including a DRAM array. DRAM cells are very tightly packed, so that when the DRAM gate length is patterned to a dimension that is greater than the final dimension, the rest of the cell must be adjusted to the greater dimension. Then, when the gate length is reduced, there is wasted space in the cell.
The art would benefit from a technique that permitted gates in a DRAM array to be etched to the final dimension and then reduced the gates in the logic regions outside the DRAM array.
The invention relates to a method of patterning the gate layer on a MOSFET integrated circuit in which the gate stack is first patterned to a gate length appropriate for one portion of the circuit and the remainder of the gates are then reduced in length to a final, smaller, value.
A feature of the invention is the use of a thin layer of silicon to improve the edge definition of the reduced gates in a wet etch.
Another feature of the invention is the use of a wet etch that permits accurate width control.
Another feature of the invention is the reduction of gate lengths uniformly across a circuit.